1. Field of Invention
The invention relates to a page-write indicator for a volatile memory. This invention relates to memories that possess a page-write mode, especially E.sup.2 PROM, EPROM and Flash EPROM floating-gate memories.
2. Discussion of the Related Art
Writing in a floating-gate memory is a relatively lengthy process in terms of time. To overcome this drawback, the manufacturers have created a mode of sequential writing also known as the page-write mode wherein a page of data is loaded at one time. In page-write mode, all the bytes located on one and the same line of words of the memory array are addressed successively in being stored in volatile registers. Then, when all the volatile registers have received their bytes, the contents of all the registers are written simultaneously on the word line. Since the time taken for writing in the memory is about 2 ms for an E.sup.2 PROM memory and since the time taken for writing in the register is smaller than 100 ns, if 64-word lines are available in the memory array, then the memory programming time is divided by 64, which is a considerable advantage.
An improvement to this system has been made in order to enable the writing of incomplete word lines. Indeed, in certain applications the user may be satisfied with writing incomplete pages, for example to save data in the event of the malfunctioning of an electronic system. Here, the manufacturers have devised a time lag system to activate the operation of writing in the memory array. These memories then function as follows:
at each input of a byte into a register, a time lag circuit is reset; PA1 when the time lag circuit has counted out a period, predefined by the manufacturer, of about 100 .mu.s, then the writing is activated.
A major drawback arises out of the time lag circuit because the microprocessor that writes in the memory may be interrupted by a priority task whose duration may overlap the period of the time lag. A simple solution using one time lag circuit has been implemented, and this is what now constitutes the prior art.
FIG. 1 shows the circuit for activating the writing of pages in an electrically programmable non-volatile memory according to the prior art. An edge detection circuit 1 receives a word write signal WE and gives a resetting signal INIT. The time lag circuit 2 receives, firstly, the resetting signal INIT given by the detection circuit 1 and, secondly, a page-write signal /ECRP indicating that the circuit is in page-write mode. This time lag circuit 2 gives a state bit at an output, this state bit indicating whether a time lag is in progress or whether the time lag has ended. The output of the time lag circuit 2 is connected so as to serve firstly as an indicator in a state register of the memory and secondly as a page-writing activation signal.
As shown in FIG. 1, the time lag circuit is reset when the page-writing signal /ECRP is in the high state. Then, as soon as the page-writing signal /ECRP goes to the low state, the time lag circuit 2 activates its time lag. Whenever a word-writing operation is detected, the detection circuit gives a pulse on the resetting signal NIT which resets the time lag of the time lag circuit 2. When the time lag is over, the bit given at output of the time lag circuit changes its state, indicating the activation of the write command at the same time as the indicator switches over to indicate that the time lag is over.
Many other variants exist in the prior art. Among others, the page-write signal /ECRP may be eliminated; in this case, it acts indirectly for example on the word-write signal WE and/or on the page-write command by means of a logic gate.
According to the prior art, the time lag circuit is reset whenever a byte is written in the memory whose output can be accessed by the microprocessor. Thus, after each interruption of the writing operation, the microprocessor can read a state register where a bit gives it the state of the time lag. This results in the following problem: it is possible, although the probability is low, that a bit which is being tested indicates that the time lag has not ended but that there is not enough time available for writing in memory.
One solution is to solve this problem by software means. The microprocessor tests the state bit a first time, then writes in the memory, and then tests the state bit again. If the second test of the state bit indicates that the time lag has not ended, then it may continue the programming. Otherwise, it must await the end of the operation for writing in memory, and then reactivate a page-write operation. However, the performance of two tests is an operation that is rather cumbersome to manage. Moreover, certain real-time systems set the use of a minimum number of instructions.